View ST70235A_1949537.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/28 october 2001 n dmt modem for cpe adsl, compatible with the following standards: - ansi t1.413 issue 2 - itu-t g.992.1 (g.dmt) - itu-t g.992.2 (g.lite) n supports either atm (utopia level 1 & 2) or bitstream interface n 16 bit multiplexed microprocessor interface (little and big endian compatibility) n analog front end management n dual latency paths: fast and interleaved n atm's phy layer: cell processing (cell delineation, cell insertion, hec) n adsl's overhead management n reed solomon encode/decode n trellis encode/decode (viterbi) n dmt mapping / demapping over 256 carriers n fine (2ppm) timing recover using rotor and adaptative frequency domain equalizing n time domain equalization n front end digital filters n 0.25 m m hcmos7 technology n 144 pin tqfp n power consumption: 0.4 watt applications routers at soho, stand-alone modems, pc modems. general description the ST70235A is the dmt modem and atm framer of the stmicroelectronics ascot? chipset. when coupled with st70134 analog front-end and an external controller running dedicated firmware, the product fulfills ansi t1.413 "issue 2" dmt adsl specification. the chip supports utopia level 1 and utopia level 2 interface. the ST70235A can be split up into two different sections. the physical one performs the dmt modulation, demodulation, reed-solomon encoding, bit interleaving and 4d trellis coding. the atm section embodies framing functions for the generic and atm transmission convergence (tc) layers. the generic tc consists of data scrambling and reed solomon error corrections, with and without interleaving. the ST70235A is controlled and programmed by an external controller (adsl transceiver con- troller, atc) that sets the programmable coeffi- cients. the firmware controls the initialization phase and carries out the consequent adaptation operations. tqfp144 full plastic (20 x 20 x 1.40 mm) order code: ST70235A ST70235A ascot tm dmt transceiver this is advance information on a new product now in development or undergoing evaluation. details are subject to change without notice. preliminary data
ST70235A 2/28 figure 1 : block diagram transient energy capabilities esd (electronic discharged) tests have been performed for the human body model (hbm) and for the charged device model (cdm). the pins of the device are to be able to withstand minimum 2000v for the hbm and minimum 250v for cdm. latch-up the maximum sink or source current from any pin is limited to 200ma to prevent latch-up. absolute maximum ratings symbol parameter min. typ. max. unit v dd 3.3 supply voltage 3.0 3.3 3.6 v v dd 1.8 supply voltage 1.62 1.8 1.98 v p tot total power dissipation 300 400 mw t amb ambient temperature 1m/s airflow 0 70 c r th j/a thermal resistivity 38 c/w i 3.3 current consumption 14 ma i 1.8 current consumption 135 ma test module data symbol timing unit vcxo dsp front-end fft/ifft rotor trellis coding generic tc interface module afe control controller atm test signals clock afe interface afe control controller bus general purpose i/os utopia mapper/ demapper reed/ solomon interface specific tc interface
ST70235A 3/28 figure 2 : pin connection 118 117 116 115 114 113 112 111 110 109 124 123 122 121 120 119 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 63 64 65 66 67 68 69 70 71 72 57 58 59 60 61 62 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 afrxd_1 afrxd_0 vdd 3.3 pdown gp_out testse trstb vss tck vdd 3.3 tms tdo tdi reserved reserved vss vdd 3.3 gp_in1 vss u_rx_refb u_tx_refb vdd 1.8 u_rxclk u_rxsoc u_rxclav u_rxenbb vss u_txclk u_txsoc u_tx_clav u_txenbb vdd 3.3 vdd 1.8 reserved reserved reserved reserved reserved vss reserved reserved reserved reserved reserved reserved vdd 3.3 reserved reserved vss ad_0 ad_1 ad_2 vdd 3.3 ad_3 ad_4 vss ad_5 ad_6 vdd 3.3 ad_7 ad_8 ad_9 vss ad_10 ST70235A 134 133 132 131 130 129 128 127 126 125 140 139 138 137 136 135 aftxd_1 aftxd_0 iddq vdd 1.8 reserved disable_comp vss comp_rout comp_vdd_1.8 vdd 3.3 ctrldata mclk clwd vss afrxd_3 afrxd_2 144 143 142 141 vdd 3.3 aftxd_3 aftxd_2 vss 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ad_11 vdd 1.8 ad_12 vss pclk vdd 3.3 ad_13 ad_14 ad_15 vss be1 ale vdd 3.3 csb wr_rdb rdyb 33 34 35 36 obc_type intb resetb vss 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 reserved vss reserved u_tx_addr_0 u_tx_addr_1 u_tx_addr_2 vdd 1.8 u_tx_addr_3 u_tx_addr_4 u_tx_data_0 u_tx_data_1 vdd 1.8 u_tx_data_2 u_tx_data_3 u_tx_data_4 u_tx_data_5 76 75 74 73 vdd 3.3 u_tx_data_6 u_tx_data_7 vss 47 48 49 50 51 52 53 54 55 56 41 42 43 44 45 46 u_rxdata_2 u_rxdata_3 vdd 1.8 u_rxdata_4 u_rxdata_5 vss u_rxdata_6 u_rxdata_7 vdd 3.3 u_rx_addr_0 u_rx_addr_1 u_rx_addr_2 u_rx_addr_3 vss u_rx_addr_4 gp_in0 37 38 39 40 vdd 3.3 u_rxdata_0 u_rxdata_1 vss
ST70235A 4/28 pin functions pin name type pad type hcmos7 bs function 1 vss 0v ground 2 ad_0 b bd8starp b data 0 3 ad_1 b bd8starp b data 1 4 ad_2 b bd8starp b address / data 2 5 vdd 3.3 (vss + 3.3v) power supply 6 ad_3 b bd8starp b address / data 3 7 ad_4 b bd8starp b address / data 4 8 vss 0v ground 9 ad_5 b bd8starp b address / data 5 10 ad_6 b bd8starp b address / data 6 11 vdd 3.3 (vss + 3.3v) power supply 12 ad_7 b bd8starp b address / data 7 13 ad_8 b bd8starp b address / data 8 14 ad_9 b bd8starp b address / data 9 15 vss 0v ground 16 ad_10 b bd8starp b address / data 10 17 ad_11 b bd8starp b address / data 11 18 vdd 1.8 (vss + 1.8v) power supply 19 ad_12 b bd8starp b address / data 12 20 vss 0v ground 21 pclk i tlcht i processor clock 22 vdd 3.3 (vss + 3.3v) power supply 23 ad_13 b bd8starp b address / data 13 24 ad_14 b bd8starp b address / data 14 25 ad_15 b bd8starp b address / data 15 26 vss 0v ground 27 be1 i tlcht i address 1 28 ale i tlcht c address latch 29 vdd 3.3 (vss + 3.3v) power supply 30 csb i tlcht i chip select 31 wr_rdb i tlcht i specifies the direction of the access cycle 32 rdyb oz bd4starp o controls the atc bus cycle termination 33 obc_type i-pd tlchtdq i atc mode selection (0 = i960; 1 = generic) 34 intb o bd4starp o requests atc interrupt service 35 resetb i tlcht i hard reset 36 vss 0v ground 37 vdd 3.3 (vss + 3.3v) power supply 38 u_rxdata_0 oz bd8starp b utopia rx data 0 39 u_rxdata_1 oz bd8starp b utopia rx data 1 40 vss 0v ground
ST70235A 5/28 41 u_rxdata_2 oz bd8starp b utopia rx data 2 42 u_rxdata_3 oz bd8starp b utopia rx data 3 43 vdd 1.8 (vss + 1.8v) power supply 44 u_rxdata_4 oz bd8starp b utopia rx data 4 45 u_rxdata_5 oz bd8starp b utopia rx data 5 46 vss 0v ground 47 u_rxdata_6 oz bd8starp b utopia rx data 6 48 u_rxdata_7 oz bd8starp b utopia rx data 7 49 vdd 3.3 (vss + 3.3v) power supply 50 u_rxaddr_0 i tlcht i utopia rx address 0 51 u_rxaddr_1 i tlcht i utopia rx address 1 52 u_rxaddr_2 i tlcht i utopia rx address 2 53 u_rxaddr_3 i tlcht i utopia rx address 3 54 vss 0v ground 55 u_rxaddr_4 i tlcht i utopia rx address 4 56 gp_in_0 i-pd tlchtdq i general purpose input 0 57 vdd 3.3 (vss + 3.3v) power supply 58 gp_in_1 i-pd tlchtdq i general purpose input 1 59 vss 0v ground 60 u_rxrefb o bd4starp o 8khz clock to atm device 61 u_txrefb i tlcht i 8khz clock from atm device 62 vdd 1.8 (vss + 1.8v) power supply 63 u_rx_clk i tlcht utopia rx clock 64 u_rx_soc oz bd8starp utopia rx start of cell 65 u_rxclav oz bd8starp utopia rx cell available 66 u_rxenbb i tlcht utopia rx enable 67 vss 0v ground 68 u_tx_clk i tlcht utopia tx clock 69 u_tx_soc i tlcht utopia tx start of cell 70 u_txclav oz bd8scr utopia tx cell available 71 u_txenbb i tlcht utopia tx enable 72 vdd 3.3 (vss + 3.3v) power supply 73 vss 0v ground 74 u_txdata_7 i tlcht i utopia tx data 7 75 u_txdata_6 i tlcht i utopia tx data 6 76 vdd 3.3 (vss + 3.3v) power supply 77 u_txdata_5 i tlcht i utopia tx data 5 78 u_txdata_4 i tlcht i utopia tx data 4 79 u_txdata_3 i tlcht i utopia tx data 3 80 u_txdata_2 i tlcht i utopia tx data 2 pin name type pad type hcmos7 bs function pin functions (continued)
ST70235A 6/28 81 vdd 1.8 (vss + 1.8v) power supply 82 u_txdata_1 i tlcht i utopia tx data 1 83 u_txdata_0 i tlcht i utopia tx data 0 84 u_txaddr_4 i tlcht i utopia tx address 4 85 u_txaddr_3 i tlcht i utopia tx address 3 86 vdd 1.8 (vss + 1.8v) power supply 87 u_txaddr_2 i tlcht i utopia tx address 2 88 u_txaddr_1 i tlcht i utopia tx address 1 89 u_txaddr_0 i tlcht i utopia tx address 0 90 reserved bd4starp reserved 0 91 vss 0v ground 92 reserved bd4starp reserved 1 93 reserved bd4starp reserved 2 94 reserved bd4starp reserved 3 95 vdd 3.3 (vss + 3.3v) power supply 96 reserved bd4starp reserved 4 97 reserved bd4starp reserved 5 98 reserved bd4starp reserved 6 99 reserved bd4starp reserved 7 100 reserved bd4starp reserved 8 101 reserved bd4starp reserved 9 102 vss 0v ground 103 reserved tlchtdq reserved 10 104 reserved tlchtdq reserved 11 105 reserved tlchtdq reserved 12 106 reserved tlchtdq reserved 13 107 reserved bd4starp reserved 14 108 vdd 1.8 (vss + 1.8v) power supply 109 vss 0v ground 110 reserved bd4starp reserved 15 111 reserved bd4starp reserved 16 112 tdi i-pu tlchtuq jtag i/p 113 tdo oz bd4starp jtag o/p 114 tms i-pu tlchtuq jtag made select 115 vdd 3.3 (vss + 3.3v) power supply 116 tck i-pd tlchtdq jtag clock 117 vss 0v ground 118 trstb i-pd tlchtdq jtag reset 119 testse i tlchtdq none enables scan test mode 120 gp_out o bd8starp o general purpose output pin name type pad type hcmos7 bs function pin functions (continued)
ST70235A 7/28 note: compensation cell - the comp_out pin must be connected at gnd by a 100k w resistor on board. specifications of the resistor have to meet the following requirements: 5% allowed on the value, 1% is preferred. advice is given to place the resistor so that there will be the shortest path between it and the pin. using the disable_comp signal is possible to disable the slew rate control of ios, in this mode the ios are however still funct ional, but dynamic performances are affected. an internal pull-down on disable_comp pin enables the slew rate control of ios, an external pull-up resistor (connected at 3.3v ) must be inserted in order to disable the slew rate control. 121 pdown o bd4starp o power down analog front end (reset) 122 vdd 3.3 (vss + 3.3v) power supply 123 afrxd_0 i tlcht i receive data nibble 124 afrxd_1 i tlcht i receive data nibble 125 afrxd_2 i tlcht i receive data nibble 126 afrxd_3 i tlcht i receive data nibble 127 vss 0v ground 128 clwd i tlcht i start of word indication 129 mclk i tlcht c master clock 130 ctrldata o bd4starp o serial data transmit channel 131 vdd 3.3 (vss + 3.3v) power supply 132 comp_vdd_1.8 comp_1v60 compensation cell vdd 1.8v (see note 1) 133 comp_rout o comp_1v60 none compensation cell resistor (see note 1) 134 vss comp_1v60 0v ground 135 disable_comp i tlchtdq disable compensation cell (see note 1) 136 reserved reserved 137 vdd 1.8 (vss + 1.8v) power supply 138 iddq i tlcht none test pin, active high 139 aftxd_0 o bd8starp o transmit data nibble 140 aftxd_1 o bd8starp o transmit data nibble 141 vss 0v ground 142 aftxd_2 o bd8starp o transmit data nibble 143 aftxd_3 o bd8starp o transmit data nibble 144 vdd 3.3 (vss + 3.3v) power supply table 1 : i/o driver function driver function bd4starp ttl three volt capable schmitt trigger bidirectional pad buffer, 4ma, with test pins, with active slew rate control bd8starp ttl three volt capable schmitt trigger bidirectional pad buffer, 8ma, with test pins, with active slew rate control tlchtdq ttl three volt capable input buffer with active pull-down and test pin tlchtuq ttl three volt capable input buffer with active pull-up and test pin tlcht tll three volt capable input pad buffer pin name type pad type hcmos7 bs function pin functions (continued)
ST70235A 8/28 pin summary mnemonic type bs type number of signals function power supply vdd 3.3 vdd 1.8 (vss + 3.3v) power supply (vss + 1.8v) power supply vss 0v ground atc interface ale i c 1 used to latch the address of the internal register to be accessed pclk i i 1 processor clock csb i i 1 chip selected to respond to bus cycle be1 i i 1 address 1 (not multiplexed) wr_rdb i i 1 specifies the direction of the access cycle rdyb oz o 1 controls the atc bus cycle termination intb o o 1 requests atc interrupt service ad io b 16 multiplexed address/data bus obc_type i-pd i 1 select between i960 (0) or generic (1) controller interface test access part interface tdi i-pu 1 refer to section tdo oz 1 tck i-pd 1 tms i-pu 1 trstb i-pd 1 analog front end interface afrxd i i 4 receive data nibble aftxd o o 4 transmit data nibble clwd i i 1 start of word indication pdown o o 1 power down analog front end ctrldata o o 1 serial data transmit channel mclk i c 1 master cloc atm utopia interface u_rxdata oz b 8 receive interface data u_txdata i i 8 transmit interface data u_rxaddr i i 5 receive interface address u_txaddr i i 5 transmit interface address u_rxclav oz o 1 receive interface cell available u_txclav oz o 1 transmit interface cell available u_rxenbb i-ttl i 1 receive interface enable u_txenbb i-ttl i 1 transmit interface enable u_rxsoc oz o 1 receive interface start of cell u_txsoc i-ttl i 1 transmit interface start of cell u_rxclk i-ttl c 1 receive interface utopia clock u_txclk i-ttl c 1 transmit interface utopia clock u_rxrefb o o 1 8khz reference clock to atm device u_txrefb i-ttl i 1 8khz reference clock from atm device
ST70235A 9/28 i = input, cmos levels i-pu = input with pull-up resistance, ttl levels i-pd = input with pull-down resistance, ttl levels i-ttl = input ttl levels o = push-pull output oz = push-pull output with high-impedance state io = input / tristate push-pull output bs cell = boundary-scan cell i = input cell o = output cell b = bidirectional cell c=clock main block description the following drawings describe the sequence of functions performed by the chip. dsp front-end the dsp front-end contains 4 parts in the receive direction: the input selector, the analog front-end interface, the decimator and the time equalizer. the input selector is used internally to enable test loopbacks inside the chip. the analog front-end lnterface transfers 16-bit words, multiplexed on 4 input/output signals. word transfer is carried out in 4 clock cycles. the decimator receives 16-bit samples at 8.8mhz (as sent by the analog front-end chip: st70134) and reduces this rate to 2.2mhz. the time equalizer (teq) module is a fir filter with programmable coefficients. its main purpose is to reduce the effect of inter-symbol interferences (isi) by shortening the channel impulse response. both the decimator and teq can be bypassed. in the transmit direction, the dsp front-end includes: sidelobe filtering, clipping, delay equalization and interpolation. the sidelobe filtering and delay equalization are implemented by iir filters, reducing the effect of echo in fdm systems. clipping is a statistical process limiting the amplitude of the output signal, optimizing the dynamic range of the afe. the interpolator receives data at 2.2mhz and generates samples at a rate of 8.8mhz. dmt modem this module is a programmable dsp unit. its instruction set enables the basic functions of the dmt algorithm like fft, ifft, scaling, rotor and frequency equalization (feq) in compliance with ansi t1.413 specifications. in the rx path, the 512-point fft transforms the time-domain dmt symbol into a frequency domain representation which can be further decoded by the subsequent demapping stages. in other words, the fast fourier transform process is used to transform from time domain to frequency domain (receive path). 1024 time samples are processed. after the first stage time domain equalization and fft block an ici (intercarrier interference) free information stream turns out. miscellaneous gp_in i-pd i 2 general purpose input gp_out o o 1 general purpose output resetb i i i hard reset testse i none none enable scan test mode iddq i none none test pin, active high comp_rout o none 1 compensation cell resistor disable_comp i-pd i 1 disable compensation cell mnemonic type bs type number of signals function pin summary (continued)
ST70235A 10/28 figure 3 : dsp front-end receive this stream is still affected by carrier specific channel distortion resulting in an attenuation of the signal amplitude and a rotation of the signal phase. to compensate, a frequency domain equalizer (feq) and a rotor (phase shifter) are implemented. the frequency domain equalization performs an operation on the received vector in order to match it with the associated point in the constellation. the coefficient used to perform the equalization are floating point, and may be updated by hardware or software, using a mechanism of active and inactive table to avoid dmt synchro problems.in the transmit path, the ifft reverses the dmt symbol from frequency domain to time domain. the ifft block is preceded by fine tune gain (ftg) and rotor stages, allowing for a compensation of the possible frequency mismatch between the master clock frequency and the transmitter clock frequency (which may be locked to another reference). the inverse fast fourier transform process is used to transform from frequency domain to time domain (transmit path). 256 positive frequencies are processed, giving 512 samples in the time domain. figure 4 : dsp front-end transmit figure 5 : dmt modem (rx & tx) from analog front-end in select afe i/f dec tec bypass to dmt modem from dmt modem filtering clipping afe i/f to analog front end delay equalizer out select inter- polator to/from dsp fe fft ifft feq ftg mapper demapper rotor to/from treillis coding decoding monitor feq coefficients feq update monitor indications tc
ST70235A 11/28 the fft module is a slave dsp engine controlled by the firmware running on an external controller. it works off line and communicates with other blocks through buffers controlled by the "data symbol timing unit". the dsp executes a program stored in a ram area, which constitutes a flexible element that allows for future system enhancements. dpll the digital pll module receives a metric for the phase error of the pilot tone. in general, the clock frequencies at the ends (transmitter and receiver) do not match exactly. the phase error is filtered and integrated by a low pass filter, yielding an estimation of the frequency offset. various processes can use this estimate to deal with the frequency mismatch. in particular, small accumulated phase error can be compensated in the frequency domain by a rotation of the received code constellation (rotor). larger errors are compensated in the time domain by inserting or deleting clock cycles in the sample input sequence. eventually that leads to achieve less than 2ppm between the two ends. mapper/demapper, monitor, trellis coding, feq update the demapper converts the constellation points computed by the fft to a block of bits. this means to identify a point in a 2d qam constellation plane. the demapper supports trellis coded demodulation and provides a viterbi maximum likelihood estimator. when the trellis is active, the demapper receives an indication for the most likely constellation subset to be used. in the transmit direction, the mapper receives a bit stream from the trellis encoder and modulates the bit stream on a set of carriers (up to 256). it generates coordinates for 2n qam constellation, where n < 15 for all carriers. the mapper performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy representation) which is passed to the ifft block. the trellis encoder generates redundant bits to improve the robustness of the transmission, using a 4-dimensional trellis coded modulation scheme. this feature can be disabled.the monitor computes error parameters for carriers specified in the demapper process. those parameters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection, etc. a series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame, etc. generic tc layer functions these functions relate to byte oriented data streams. they are completely described in ansi t 1.4 13. additions described in the issue 2 of this specification are also supported. the data received from the demapper may be split into two paths, one dedicated to an interleaved data flow the other one for a fast data flow. no external ram is needed for the interleaved path. the interleaving/deinterleaving is used to increase the error correcting capability of block codes for error bursts. after deinterleaving (if applicable), the data flow enters a reed-solomon error correcting code decoder, able to correct a number of bytes containing bit errors. the decoder also uses the information of previous receiving stages that may have detected the error bytes and have labelled them with an "erasure indication". each time the rs decoder detects and corrects errors in a rs codeword, an rs correction event is generated. the occurrence of such events can be signalled to the management layer.after the rs decoder, the corrected byte stream is descrambled in the pmd (physical medium dependent) descramblers. two descramblers are used, for interleaved and non-interleaved data flows. these are defined in ansi t1.413. after descrambling, the data flows enter the deframer that extracts and processes bytes to support physical layer related functions according to ansi t1.413. the adsl frames indeed contain physical layer-related information in addition to the data passed to the higher layers. in particular, the deframer extracts the eoc (embedded operations channel), the aoc (adsl overhead control) and the indicators bits and passes them to the appropriate processing unit (e.g. the transceiver controller). the deframer also performs a crc check (cyclic redundancy check) on the received frame and generates events in case of error detection.event counters can be read by management processes. the outputs of the deframer are an interleaved and a fast data streams. these data streams can either carry atm cells or another type of traffic. in the latter case, the atm specific tc layer functional block, described hereafter, is bypassed and the data stream is directly presented at the input of the interface module.
ST70235A 12/28 figure 6 : generic tc layer functions atm specific tc layer functions the 2 bytes streams (fast and slow) are received from the byte-based processing unit. when atm cells are transported, this block provides basic cell functions such as cell synchronization, cell payload descrambling, idle/unassigned cell filter, cell header error correction (hec) and detection. the cell processing happens according to itu-t i.163 standard. provision is also made for ber measurements at this atm cell level. when non cell oriented byte streams are transported, the cell processing unit is not active. the interface module collects cells (from the cell-based function module). cells are stored in fifo's (424 bytes or 8 cell wide, transmit buffers have the same size), from which they are extracted by 2 interface submodules, one providing a utopia level 1 interface and the other a utopia level 2 interface. data patx merger interleaver de-interleaver rs coding pmd scrambler pmd scrambler decoding f i framer deframer f i to atm tc indication bits aoc eoc to/from demapper fast descrambler descrambler figure 7 : atm specific tc layer functions figure 8 : interface module cell scrambler descrambler synchronizer cell scrambler descrambler synchronizer hec hec cell insertion/ filter cell insertion/ filter ber ber fast slow to interface module from generic tc level 1 utopia level 2 utopia level 1 utopia level 2 utopia fast atm slow atm from atm tc
ST70235A 13/28 dmt symbol timing unit (dstu) the dstu interfaces with various modules, like dsp frontend, fft/ifft, mapper/demapper, rs, monitor and transceiver controller. it consists of a real time and a scheduler modules. the real time unit generates a timebase for the dmt symbols (sample counter), superframes (symbol counter) and hyper-frames (sync counter). the timebases can be modified by various control features. they are continuously fine-tuned by the dpll module. the dstu schedulers execute a program, controlled by program opcodes and a set of variables, the most important of which are real time counters. the transmit and receive sequencers are completely independent and run different programs. an independent set of variables is assigned to each of them. the sequencer programs can be updated in real time. ST70235A interfaces overview see figure 9. processor interface (atc) the ST70235A is controlled and configured by an external processor across the processor interface. all programmable coefficients and parameters are loaded through this path. data and addresses are multiplexed ST70235A works in 16 bits data access, so address bit 0 is not used. address bit 1 is not multiplexed with data. it has its own pin : be1. byte access are not supported. access cycle read or write are always in 16 bits data wide, ie bit address a0 is always zero value. the interrupt request pin to the processor is intb, and is an open drain output. the ST70235A supports both little and big endian. the default feature is big endian. generic interface this interface is suitable for a number of processors using a multiplexed address/data bus. in this case, synchronization of the input signals with pclk pin is not necessary. figure 10 : generic processor interface write timing cycle figure 9 : ST70235A interfaces afe interface to adsl line (st70134) reset jtag clock processor interface (atc) digital interface utopia ST70235A ale csb address/data wrb rdyb mclk t alew 1 1: rdb = wr_rdb is high. t ale2cs t avs t avh t cs2wr t wr2mclk t wr2rdy t csre t wr2d t rdy2wr t rdy2cs t mclk
ST70235A 14/28 figure 11 : generic processor interface read timing cycle generic processor interface cycle timing all ac characteristics are indicated for a 100pf capacitive load.cycle timing for generic interface. the timing are generally presented with the write signal, but as shown on the read diagram, they are also valid for the read signal, so for example the trdy2wr timing is the same as what can be trdy2rd. table 2 : cycle timing symbol parameters minimum maximum unit tcsre access time 900 m s talew ale pulse width 12 ns tavs address valid setup time 10 ns tavh address valid hold time 10 ns tale2cs ale to csb 0 ns tale2z ale to high z state of bus 50 ns tcs2wr csb to wrb 0 ns tcs2rd csb to rdb 0 ns twr2d wr to data 15 ns twr2rdy wr to dy asserted 60 ns trd2rdy rd to rdy asserted 60 ns trdy2wr rdyb to wrb 0 ns trdy2rd rdyb to rdb 0 ns tdvs data valid setup time 10 ns tdvh data valid hold time 1/2 tmclk tmclk ns trdy2cs rdyb to csb 0 ns tmclk master clock timing : cf specifications twr2mclk setup time according to the master clock 10 ns trd2mclk setup time according to the master clock 10 ns ale csb address/data rdb rdyb mclk t alew 1 1: wrb = be1 is high. t ale2cs t avs t avh t cs2rd t rd2mclk t rd2rdy t csre t dvs t dvh t rdy2rd t rdy2cs t wrw t mclk t ale2z
ST70235A 15/28 generic processor interface pins and functional description digital interface atm or serial digital interface for data to the loop before modulation and from the loop after demodulation. this interface collects cells (from the cell based function module) or a byte stream (from the deframer). cells are stored in a fifo, 2 interfaces submodules can extract data from the fifo. 2 kinds of interface are allowed: C utopia level 1 C utopia level 2 the interface selection is programmed by writing the utopia phy address register. only one interface can be enabled in a ST70235A configuration. utopia level 1 supports only one phy device. utopia level 2 supports multi-phy devices (see utopia level 2 specifications). each buffer provides storage for 8 atm cells (both directions for fast and interleaved channel). the utopia level 2 supports point to multipoint configurations by introducing an addressing capability and by making distinction between polling and selecting a device. figure 12 : receive interface figure 13 : transmit interface utopia level 1 interface the atm forum takes the atm layer chip as a reference. it defines the direction from atm to physical layer as the transmit direction. the direction from physical layer to atm is the receive direction. figures 12 & 13 show the interconnection between atm and phy layer devices, the optional signals are not supported and not shown. the utopia interface transfers one byte in a single clock cycle, as a result cells are transformed in 53 clock cycles. both transmit and receive are synchronized on clocks generated by the atm layer chip, and no specific relationship between receive and transmit clocks is required. in this mode, the ST70235A can only support one data flow : either interleaved or fast. name type function ad[0..15] i/o multiplexed address / data bus ale i address latch enable rdb i read cycle indication wrb i write cycle indication csb i chip select rdyb oz bus cycle ready indication intb o interrupt phy receive rxref* rxclav rxenb* rxclk rxdata rxsoc cell receive phy atm 8 phy transmit txref* txclav txenb* txclk txdata txsoc cell transmit phy atm layer 8
ST70235A 16/28 figure 14 : timing (utopia 2 receive interface) pin description note 1. active low signal when rxenb is asserted, the ST70235A reads data from its internal fifo and presents it on rxdata and rxsoc on each low-to-high transition of rxclk, ie the atm layer chip samples all rxdata and rxsoc on the rising edge of rxsoc on the rising edge of rxclk. name type meaning usage remark rxclav o receive cell available signals to the atm chip that the ST70235A has a cell ready for transfer remains active for the entire cell transfer rxenb 1 i receive enable signals to the ST70235A that the atm chip will sample and accept data during next clock cycle rxdata and rxsoc could be tri-state when rxenb* is inactive (high). active low signal rxclk i receive byte clock gives the timing signal for the transfer, generated by atm layer chip. rxdata o receive data (8bits) atm cell data, from ST70235A chip to atm chip, byte wide. rx data [7] is the msb. rxsoc o receive start cell identifies the cell boundary on rxdata indicate to the atm layer chip that rxdata contains the first valid byte of a cell rxref 1 o reference clock 8 khz clock transported over the network active low signal 1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 n+3 1f n-3 1f n+1 1f n-1 1f n 1f 1f n-1 1f n-3 1f n-3 1f n+1 1f n+2 n-3 n+1 n-1 n n+3 n-1 n-3 n-3 n+1 rxclk rxaddr rxclav rxenb* rxdata rxsoc p41 p42 p43 p44 p45 p46 p47 p48 xx h1 h2 h3 cell transmission from: phy n phy n-3 polling: polling detection selection polling
ST70235A 17/28 pin description note 1. active low signal the ST70235A samples txdata and txsoc signals on the rising edge of txclk, if txenb is asserted. txclk, rxclk, ac electrical characteristics txdata, txsoc, txaddr, txenb, ac electrical characteristics note: tx data hold time is 1.2ns. all the utopia hold time are guarantee by design. rxdata, rxsoc, rxclav, txclav, ac electrical characteristics name type meaning usage remark txclav o transmit cell available signals to the atm chip that the physical layer chip is ready to accept a complete cell remains active for the entire cell transfer txenb 1 i transmit enable signals to the ST70235A that txdata and txsoc are valid txclk i transmit byte clock gives the timing signal for the transfer, generated by atm layer chip. txdata i transmit data (8bits) atm cell data, from atm layer chip to ST70235A, byte wide. txdata [7] is the msb. txsoc i transmit start of cell identifies the cell boundary on txdata txdata contains the first valid byte of the cell. txref 1 i reference clock 8khz clock from the atm layer chip symbol parameters minimum maximum unit f clock frequency 1.5 25 mhz tc clock duty cycle 40 60 % tj clock peak to peak jitter 5 % trf clock rise fall time 4 ns l load 100 pf symbol parameters minimum maximum unit t5 input set-up time to txclk 10 ns t6 hold time to txclk 1 ns l load 100 pf symbol parameters minimum maximum unit t7 input set-up time to txclk 10 ns t8 hold time to tx clk 1 ns t9 signal going low impedance to rxclk 10 ns t10 signal going high impedance to rxclk 0 ns t11 signal going low impedance to rxclk 1 ns t12 signal going high impedance to rxclk 1 ns l load 100 pf
ST70235A 18/28 rxaddr, rxenb, ac electrical characteristics figure 15 : timing (utopia 2 transmit interface) symbol parameters minimum maximum unit t5 input setup time to rxclk 10 ns t6 hold time to rxclk 1 ns l load 100 pf figure 16 : timing specification (utopia 2) 1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 n-1 1f n+1 1f n1f n+3 1f n+2 1f 1f n 1f n+3 1f n+3 1f n-2 1f n-3 n+1 n n+3 n+2 n-1 n n+3 n+3 n+1 txclk txaddr txclav txenb* txdata txsoc p45 p46 p47 p48 h1 h3 h4 cell transmission from: phy n phy n+3 polling: polling detection selection polling n-2 h2 clock signal (at input) signal (highz) t5, t7 t6, t8 t11 t9 t12 t10
ST70235A 19/28 digital interface utopia level 2 interface the atm forum takes the atm layer chip as a reference. it defines the direction from atm to physical layer as the transmit direction. the direction from physical layer to atm is the receive direction. figure 17 shows the interconnection between atm and phy layer devices, the optional signals are not supported and not shown. the utopia interface transfers one byte in a single clock cycle, as a result cells are transferred in 53 clock cycles.both transmit and receive interfaces are synchronized on clocks generated by the atm layer chip, and no specific relationship between receive and transmit clock is assumed, they must be regarded as mutually asynchronous clocks. flow control signals are available to match the bandwidth constraints of the physical layer and the atm layer. the utopia level 2 supports point to multipoint configurations by introducing on addressing capability and by making a distinction between polling and selecting a device: C the atm chip polls a specific physical layer chip by putting its address on the address bus when the enb* line is asserted. the addressed physi- cal layer answers the next cycle via the clav line reflecting its status at that time. C the atm chip selects a specific physical layer by putting its address on the address bus when the enb* line is deasserted and asserting the enb* line on the next cycle. the addressed physical layer chip will be the target or source of the next cell transfer (see figure 17). utopia level 2 signals the physical chip sends cell data towards the atm layer chip. the atm layer chip polls the status of the fifo of the physical layer chip. the cell exchange proceeds like: a) the physical layer chip signals the availability of a cell by asserting rxclav when polled by the atm chip. b) the atm chips selects a physical layer chip, then starts the transfer by asserting rxenb*. c) if the physical layer chip has data to send, it puts them on the rxdata line the cycle after it sampled rxenb* active. it also advances the offset in the cell. if the data transferred is the first byte of a cell, rxsoc is 1b at the time of the data transfer, 0b otherwise. d) the atm chip accepts the data when they are available. if rxsoc was 1b during the transfer, it resets its internal offset pointer to the value 1, otherwise it advances the offset in the cell. ST70235A utopia level 2 mphy operation utopia level 2 mphy operation can be done by various interface schemes. the ST70235A supports only the required mode, this mode is referred to as "operation with 1 txclav and 1 rxclav". phy device identification the ST70235A holds 2 phy layer utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. the associated phy address is specified by the phy_addr_x fields in the utopia phy address register. figure 17 : signal at utopia level 2 interface phy receive rxaddr rxclav rxenb* rxclk rxdata rxsoc phy atm 8 5 rxref* atm receive phy transmit txaddr txclav txenb* txclk txdata txsoc 8 5 txref* atm transmit 1 1
ST70235A 20/28 beware that an incorrect address configuration may lead to bus conflicts. a feature is defined to disable (tri-state) all outputs of the utopia interface. it is enabled by the tri_state_en bit in the rx_interface control register. pin description utopia 2 (receive interface) note *active low signal pin description utopia 2 (transmit interface) note *active low signal name type meaning usage remark rxclav o receive cell available signals to the atm chip that the stlc60135 has a cell ready for transfer remains active for the entire cell transfer rxenb* i receive enable signals to the physical layer that the atm chip will sample and accept data during next clock cycle rxdata and rxsoc could be tri-state when rxenb* is inactive (high) rxclk i receive byte clock gives the timing signal for the transfer, generated by atm layer chip. rxdata o receive data (8 bits) atm cell data, from physical layer chip to atm chip, byte wide. rxsoc o receive start cell identifies the cell boundary on rxdata indicate to the atm layer chip that rxdata contains the first valid byte of a cell. rxaddr i receive address (5 bits) use to select the port that will be active or polled rxref * o reference clock 8khz clock transported over the network name type meaning usage remark txclav o transmit cell available signals to the atm chip that the physical layer chip is ready to accept a cell remains active for the entire cell transfer txenb* i transmit enable signals to the physical layer that txdata and txsoc are valid txclk i transmit byte clock gives the timing signal for the transfer, generated by atm layer chip. txdata i transmit data (8 bits) atm cell data, to physical layer chip to atm chip, byte wide. txsoc i transmit start of cell identifies the cell boundary on txdata txaddr i transmit address (5 bits) use to select the port that will be active or polled txref * i reference clock 8khz clock from the atm layer chip
ST70235A 21/28 analog front end control interface the analog front end interface is designed to be connected to the st70134 analog front end component. transmit interface the 16 bit words are multiplexed on 4 aftxd output signals. as a result 4 cycles are needed to transfer 1 word. refer to table 1 for the bit/pin allocation for the 4 cycles. the first of 4 cycles is identified by the clwd signal. refer to figure 18. the ST70235A fetches the 16 bit word to be multiplexed on aftxd from the tx digital front-end module. receive interface the 16 bit receive word is multiplexed on 4 afrxd input signals. as a result 4 cycles are needed to transfer 1 word. refer to table 2 for the bit / pin allocation for the 4 cycles. the first of 4 cycles is identified by the clwd must repeat after 4 mclk cycles. figure 18 : transmit word timing diagram figure 19 : receive word timing diagram cycle1 cycle0 cycle2 cycle3 test0 test1 test2 test3 mclk clwd aftxd gp_out cycle1 cycle0 cycle2 cycle3 test0 test1 test2 test3 mclk clwd afrxd gp_in(0)
ST70235A 22/28 figure 20 : transmit interface table 3 : transmitted bits assigned to signal / time slot figure 21 : receive interface mclk aftxd tv mclk afrxd ts th clwd tc cycle 0 cycle 1 cycle 2 cycle 3 aftxd[0] b0 b4 b8 b12 aftxd[1] b1 b5 b9 b13 aftxd[2] b2 b6 b10 b14 aftxd[3] b3 b7 b11 b15 table 4 : transmitted bits assigned to signal / time slot cycle 0 cycle 1 cycle 2 cycle 3 afrxd[0] b0 b4 b8 b12 afrxd[1] b1 b5 b9 b13 afrxd[2] b2 b6 b10 b14 afrxd[3] b3 b7 b11 b15 table 5 : master clock (mclk) ac electrical characteristics symbol parameter minimum typical maximum unit f clock frequency 35.328 mhz tper clock period 28.3 ns th clock duty cycle 40 60 % table 6 : aftxd, aftxed, clwd ac electrical characteristics symbol parameter minimum typical maximum unit tv data valid time 0 13 ns tc data valid time 0 10 ns table 7 : afrxd ac electrical characteristics symbol parameter minimum typical maximum unit ts data setup time 5 ns th data hold time 5 ns
ST70235A 23/28 tests, clock, jtag interface C mclk: master clock (35.328mhz) generated by vcxo C atm receive interface, asynchronous clock gen- erated by utopia master C atm transmit interface, asynchronous clock generated by utopia master C atc clock (pclk): external asynchronous clock (synchronous with atc in case of i960 specific interface) jtag tp interface: standard test access port, used with the boundary scan for chip and board testing. this jtag tap interface consists in 5 signals: tdi, tdo, tck & tms. tsrtb: test reset, reset the tap controller. trstb is an active low signal. table 8 : boundary scan chain sequence signal name sequence number bs type ad[0] io2 b ad[1] io3 b ad[2] io4 b ad[3] io6 b ad[4] io7 b ad[5] io9 b ad[6] io10 b ad[7] io12 b ad[8] io13 b ad[9] io14 b ad[10] io16 b ad[11] io17 b ad[12] io19 b pclk io21 c ad[13] io23 b ad[14] io24 b ad[15] io25 b be1 io27 i ale io28 c csb io30 i wr_rdb io31 i rdyb io32 b obc_type io33 i intb io34 o resetb io35 i u_rxdata[0] io38 b u_rxdata[1] io39 b u_rxdata[2] io41 b u_rxdata[3] io42 b u_rxdata[4] io44 b u_rxdata[5] io45 b u_rxdata[6] io47 b u_rxdata[7] io48 b u_rxaddr[0] io50 i u_rxaddr[1] io51 i u_rxaddr[2] io52 i u_rxaddr[3] io53 i u_rxaddr[4] io55 i gp_in[0] io56 i gp_in[1] io58 i u_rxrefb io60 o u_txrefb io61 i u_rxclk io63 c u_rxsoc io64 i u_rxclav io65 o u_rxenb io66 i u_txclk io68 c u_txsoc io69 i u_txclav io70 o u_txenb io71 i u_txdata[7] io74 i u_txdata[6] io75 i table 8 : boundary scan chain sequence signal name sequence number bs type
ST70235A 24/28 general purpose i/o register (0x40) bits from 3 to 15 are reserved reset initialization the ST70235A supports two reset modes: C a 'hardware' reset is activated by the resetb pin (active low). a hard reset occurs when a low input value is detected at the resetb input. the low level must be applied for at least 1ms to guarantee a correct reset operation. all clocks and power supplies must be stable for 200ns prior to the rising edge of the r esetb signal. C 'soft' reset activated by the controller write access to a soft reset configuration bit. the reset process takes less than 10000 mclk clock cycles. u_txdata[5] io77 i u_txdata[4] io78 i u_txdata[3] io79 i u_txdata[2] io80 i u_txdata[1] io82 i u_txdata[0] io83 i u_txaddr[4] io84 i u_txaddr[3] io85 i u_txaddr[2] io87 i u_txaddr[1] io88 i u_txaddr[0] io89 i reserved 0 io90 o reserved 1 io92 o reserved 2 io93 o reserved 3 io94 o reserved 4 io96 o reserved 5 io97 o reserved 6 io98 o reserved 7 io99 o reserved 8 io100 none reserved 9 io101 o reserved 10 io103 i reserved 11 io104 i reserved 12 io105 i reserved 13 io106 i reserved 14 io107 o reserved 15 io110 o reserved 16 io111 o tdi io112 none tdo io113 none tms io114 none tck io116 none trstb io118 none testse io119 c gp_out io120 o table 8 : boundary scan chain sequence signal name sequence number bs type pdown io121 o afrxd[0] io123 i afrxd[1] io124 i afrxd[2] io125 i afrxd[3] io126 i clwd io128 i mclk io129 c ctrldata io130 o disable_comp io135 i iddq io138 c aftxd[0] io139 none aftxd[1] io140 none aftxd[2] io142 none aftxd[3] io143 none field type position bits length function gp_in r [0,1] 2 sampled level on pins gp_in gp_out rw [2] 1 output level on pins gp_out table 8 : boundary scan chain sequence signal name sequence number bs type
ST70235A 25/28 electrical specifications generic dc electrical characteristics the values presented in the following table apply for all inputs and/or outputs unless otherwise specified. all voltages are referenced to v ss , unless otherwise specified, positive current is towards the device. io buffers generic dc characteristics input/ output ttl generic characteristics the values presented in the following table apply for all ttl inputs and/or outputs unless otherwise specified. * the reference current is dependent on the exact buffer chosen and is a part of the buffer name. the available values are 4 an d 8ma. symbol parameter test condition minimum typical maximum unit i in input leakage current v in = v ss , v dd no pull up /pull down -4 4 m a i oz tristate leakage current v in = v ss , v dd no pull up /pull down -4 4 m a i pu pull up current v in = v ss -15 -66 -125 m a i pd pull down current v in = v dd 15 66 125 m a r pu pull up resistance v in = v ss 50 k w r pd pull down resistance v in = v dd 50 k w symbol parameter test condition minimum typical maximum unit v il low level input voltage 0.8 v v ih high level input voltage 2.0 v v hy schmitt trigger hysteresis slow edge < 1v/ m s 0.4 0.7 v v ol low level output voltage i out = xma* 0.4 v v oh high level output voltage i out = xma* 2.4 v
ST70235A 26/28 tqfp144 package mechanical data figure 22 : package outline tqfp144 dimension millimeter inch minimum typical maximum minimum typical maximum a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.0067 0.0087 0.011 c 0.09 0.20 0.0035 0.008 d 22.00 0.866 d1 20.00 0.787 d3 17.50 0.689 e 0.50 0.020 e 22.00 0.866 e1 20.00 0.787 e3 17.50 0.689 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0 (minimum), 7 (maximum) c b a1 a2 a l k l1 0,25 mm .010 inch gage plane 0.03 inch seating plane 0,076 mm 144 109 e 37 72 1 36 73 108 d3 d1 d e3 e1 e
ST70235A 27/28
ST70235A information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states http://www.st.com 28/28 ST70235A.ref

▲Up To Search▲

Price & Availability of ST70235A

	To Download ST70235A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .